1. Field of the Invention
This invention relates to self-refreshing DRAMs and, more particularly, to a test mode circuit that tests for missed internal refresh cycles.
2. Prior Art
A self-refreshing DRAM uses dynamic RAM memory cells which must be periodically refreshed. If a DRAM cell is not refreshed within a certain period of time, memory cells lose their charge and may provide erroneous data when read. Previously, it was not possible to test or to characterize a self-refresh DRAM with regard to its ability to ensure that all refresh cycles were properly executed. Consequently, a need exists for a technique to test or characterize a self-refresh DRAM with regard to its ability to ensure that all refresh cycles were properly executed.
In order to be able to test or characterize a self-refreshing dram to ensure that refresh cycles are properly executed, it is advantageous to incorporate a circuit that indicates if any attempts at an internal refresh have failed to execute.
It is therefore an object of the invention to provide a counter, which is incremented whenever an internal refresh is requested and a prior internal refresh request has not yet been completed. Provision is made to read out the count, and to reset the count. By reading out the count an indication is obtained of how many refresh requests were missed, and by using arbitrary input patterns the robustness of the self-refresh circuitry can be tested and confirmed.
A latch or similar storage element is set whenever an internal refresh cycle is requested. The latch is reset when a refresh cycle begins execution. If an internal refresh request occurs and the latch is still set, the counter is incremented to indicate a missed internal refresh cycle. Circuitry is also provided which allows the counter to be cleared, for example, upon application of a suitable test mode pattern.
The present invention provides a circuit for detecting missed refresh cycles of a self-refreshing DRAM. The circuit includes a refresh-request storage element that has an output terminal at which is provided an output signal that is set upon receipt of an internal refresh request control signal to initiate an internal refresh cycle. The output of the storage element is reset upon initiation of an internal refresh cycle. IN one preferred embodiment, the storage element is a latch circuit such an R/S flip-flop circuit.
The circuit for detecting missed refresh cycles includes a refresh miss detector that provides an output pulse when the refresh request signal is received concurrent with the refresh request storage element being set.
The circuit for detecting missed refresh cycles also includes a refresh miss counter that is incremented with an output pulse of the refresh miss detector and that accumulates a count of missed refresh cycles.
The output terminal of the refresh-request storage element is connected to one input terminal of an arbitration circuit. Another input terminal of the arbitration circuit receives an external row-access-select (xras_req) signal. The output terminal of the arbitration circuit provides either a refresh cycle activation signal (ref_time_b) or an external row-access-select (xras_time_b) signal. The refresh cycle activation signal (ref_time_b) resets the refresh-request storage element.
The invention further provides a two-bus input multiplexer having an output terminals that are connected to data output terminals of the self-refreshing DRAM. The multiplexer has one set of input terminals that are connected to respective xe2x80x9cbitxe2x80x9d output terminal of the counter. The multiplexer has another set of input terminals that are connected to data  less than 7:0 greater than  out put signals of the DRAM.
The refresh miss detector includes a two-input AND circuit that has a first input terminal coupled to the ref_req input terminal and a second input terminal coupled to the output terminal of the storage element such that the AND circuit provides an output signal when a refresh_req signal is received and the storage element is set. The refresh miss counter is reset by a signal that is provided when a suitable test mode pattern is provided to data input terminals of the self refreshing DRAM.
A data pattern detector detects when a suitable test mode pattern is provided to data input terminals of the self refreshing DRAM and provides a reset signal to reset the refresh miss counter.
The present invention also provides a method for testing for refresh misses in a self-refreshing DRAM. The method includes the steps of setting an output terminal of a storage device upon receipt of an internal refresh request control signal that is intended to initiate an internal refresh cycle; normally resetting the output terminal of the storage device upon initiation of the internal refresh cycle; detecting that an internal refresh cycle has not occurred and providing a refresh-missed output pulse indicative thereof; and incrementing a refresh miss counter with the refresh-missed pulses to accumulate a count of missed internal refresh cycles.
The step of detecting that an internal refresh cycle has not occurred includes detecting that a refresh request signal is received concurrent with the refresh request storage element being set.
The step of normally resetting the output terminal of the storage device upon initiation of the internal refresh cycle includes the steps of: arbitrating between an internal refresh request signal and an external request signal; and providing a refresh cycle activation signal to reset the storage device.
The method includes the step of connecting signals representative of the accumulated count of missed internal refresh cycles to output pins of the DRAM.
The step of detecting that an internal refresh cycle has not occurred includes logically combining in an AND function a refresh request signal and a concurrent set status of the storage device.